The present invention relates to the adaptive dynamic management of computer system operations, and more specifically to the dynamic voltage and frequency scaling (DVFS) of microprocessors.
Generally, microprocessor performance gain is achieved by increasing the microprocessor (clock) frequency. But this goes along with the requirement of a higher effort in production and development costs, finally resulting in higher asset costs for computer systems. Permanent rise of the nominal frequency goes along with high requirements on cooling techniques and materials. Many microprocessor manufacturers dimension the maximal microprocessor frequency rather conservative to ensure operational stability and make some worst-case assumptions, so that for example environmental setups like those provided in air-conditioned rooms for huge server clusters are feasible.
Power consumption and the associated heat generation of modern microprocessors are key design issues in the development process of computer systems, especially when the available space is very limited like in desktop systems or blade centers. Many mechanisms exist in contemporary microprocessors to vary its power consumption, e.g. by explicitly decreasing or increasing frequency and voltage. Many modern microprocessors provide such DVFS mechanisms. Enhanced SpeedStep is one of those and supported by various Intel microprocessors.
An important feature of contemporary microprocessors is the availability of a multitude of performance counters providing detailed information about workload characteristics, e.g. information about retired (completed) Instructions Per clock Cycle (IPC), processor cache misses, etc.
Nominal microprocessor frequencies used in computer systems are based on worst case assumptions concerning certain characteristics; e.g., ambient temperature and power demand of workloads. In general, the microprocessor hardware allows frequencies that are significantly higher than the nominal frequencies. Thermal limitations are frequently alleviated by modern cooling techniques or an air conditioned setting of the system. Microprocessor power consumption depends significantly on the type of workload. However, in typical customer scenarios, the worst case assumptions do not occur simultaneously.
Various approaches to autonomously reduce microprocessor power consumption exist when there has been no or little system utilization detected for some period of time. A metric often used for workload characterization is the IPC number. It allows characterizing the microprocessor performance independent of its clock frequency. A method for prediction of workload phase duration and characterization is proposed in C. Isci et al “Long-Term Workload Phases: Duration Predictions and Applications to DVFS”, IEEE Micro, Vol. 25, 5/2005, pp. 39-51. That work mainly concentrates on a workload estimation using a last-value prediction. A gradient-based workload prediction technique based on linear regression is described in W. L. Bircher et al “Runtime Identification of Microprocessor Energy Saving Opportunities”, Proc. of the ILSPED 2005, pp. 275-280.
The so-called Foxton technology as used in the Intel Itanium2 is an example for a mechanism used in contemporary microprocessors to increase frequency and voltage above the default values by using a temporary overclocking on the chip level. Descriptions of the Foxton technology are given in R. McGowen et al “Power and temperature control on a 90-nm Itanium family processor” IEEE Journal of Solid State Signals Vol. 1, 1/2006, pp. 229-237 and T. Fischer et al “A 90-nm variable frequency clock system for a power-managed itanium architecture processor”, IEEE Journal of Solid State Signals Vol. 1, 1/2006, pp. 218-228.
Existing DVFS solutions mainly focus on the improvement of microprocessor energy efficiency and not boosting of its performance. They optimize microprocessor power consumption with only minimal impact on the performance of the workload currently executed by the microprocessor.